One of the promising dual channel complementary-metal oxide semiconductor (CMOS) integration schemes for future technologies is to use tensile-strained silicon (Si) for n-channel field-effect transistors (n-FETs) and compressively-strained silicon germanium (SiGe) grown on a Si substrate for p-channel FETs (p-FETs). However, a conventional strategy to fabricate both analog (I/O) and logic devices in Si/SiGe dual channel CMOS suffers from performance degradation of the SiGe p-FET due to a large amount of interface trap density (Dit), which is attributed to undesired germanium oxide (GeOx) formation in the interfacial layer as well as germanium (Ge) pile-up at the surface. See, for example, Lee et al., “Selective GeOx-Scavenging from Interfacial Layer on Si1-xGex Channel for High Mobility Si/Si1-xGex CMOS Application,” 2016 IEEE Symposium on VLSI Technology (June 2016) (2 pages) (GeOx formation in the interfacial layer) and Lee et al., “Engineering the Electronic Defect Bands at the Si1-xGex/IL Interface: Approaching the Intrinsic Carrier Transport in Compressively-Strained Si1-xGex pFETs,” 2016 IEEE International Electron Devices Meeting (IEDM) (December 2016) (4 pages) (Ge pile-up).
Therefore, techniques for improving analog and logic device performance in Si/SiGe dual channel CMOS would be desirable.